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? semiconductor components industries, llc, 2006 march, 2006 ? rev. 4 1 publication order number: ne5230/d ne5230, sa5230, se5230 low voltage operational amplifier the ne5230 is a very low voltage operational amplifier that can perform with a voltage supply as low as 1.8 v or as high as 15 v. in addition, split or single supplies can be used, and the output will swing to ground when applying the latter. there is a bias adjusting pin which controls the supply current required by the device and thereby controls its power consumption. if the part is operated at 0.9 v supply voltages, the current required is only 110 a when the current control pin is left open. even with this low power consumption, the device obtains a typical unity gain bandwidth of 250 khz. when the bias adjusting pin is connected to the negative supply, the unity gain bandwidth is typically 600 khz while the supply current is increased to 600 a. in this mode, the part will supply full power output beyond the audio range. the ne5230 also has a unique input stage that allows the common ? mode input range to go above the positive and below the negative supply voltages by 250 mv. this provides for the largest possible input voltages for low voltage applications. the part is also internally ? compensated to reduce external component count. the ne5230 has a low input bias current of typically 40 na, and a large open ? loop gain of 125 db. these two specifications are beneficial when using the device in transducer applications. the large open ? loop gain gives very accurate signal processing because of the large ?excess? loop gain in a closed ? loop system. the output stage is a class ab type that can swing to within 100 mv of the supply voltages for the largest dynamic range that is needed in many applications. the ne5230 is ideal for portable audio equipment and remote transducers because of its low power consumption, unity gain bandwidth, and 30 nv/ hz noise specification. features ? works down to 1.8 v supply voltages ? adjustable supply current ? low noise ? common ? mode includes both rails ? v out within 100 mv of both rails ? pb ? free packages are available applications ? portable precision instruments ? remote transducer amplifier ? portable audio equipment ? rail ? to ? rail comparators ? half ? wave rectification without diodes ? remote temperature transducer with 4.0 to 20 ma output transmission http://onsemi.com pin connections see detailed ordering and shipping information in the package dimensions section on page 16 of this data sheet. ordering information (top view) pdip ? 8 n suffix case 626 soic ? 8 d suffix case 751 1 2 3 45 6 7 8 nc ? in +in output bias adj. v ee v cc nc ? + n, d packages 1 8 1 8 see general marking information in the device marking section on page 16 of this data sheet. device marking information
ne5230, sa5230, se5230 http://onsemi.com 2 maximum ratings rating symbol value unit single supply voltage v cc 18 v dual supply voltage v s 9 v input voltage (note 1) v in 9 (18) v differential input voltage (note 1) v s v common ? mode voltage (positive) v cm v cc + 0.5 v common ? mode voltage (negative) v cm v ee ? 0.5 v power dissipation (note 2) p d 500 mw thermal resistance, junction ? to ? ambient n package d package r ja 130 182 c/w operating junction temperature (note 2) t j 150 c operating temperature range ne sa se t a 0 to 70 ? 40 to 85 ? 40 to 125 c 80 output short ? circuit duration to either power supply pin (notes 2 and 3) indefinite s storage temperature t stg ? 65 to 150 c lead soldering temperature (10 sec max) t sld 230 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. can exceed the supply voltages when v s ? 7.5 v (15 v). 2. the maximum operating junction temperature is 150 c. at elevated temperatures, devices must be derated according to the package thermal resistance and device mounting conditions. derate above 25 c at the following rates: n package at 7.7 mw/ c d package at 5.5 mw/ c. 3. momentary shorts to either supply are permitted in accordance to transient thermal impedance limitations determined by the pa ckage and device mounting conditions. recommended operating conditions characteristic value unit single supply voltage 1.8 to 15 v dual supply voltage 0.9 to 7.5 v common ? mode voltage (positive) v cc + 0.25 v common ? mode voltage (negative) v ee ? 0.25 v temperature ne grade sa grade se grade 0 to +70 ? 40 to +85 ? 40 to +125 c
ne5230, sa5230, se5230 http://onsemi.com 3 dc and ac electrical characteristic unless otherwise specified, 0.9v vs 7.5 v or equivalent single supply, r l = 10 k , full input common ? mode range, over full operating temperature range. characteristic symbol test conditions bias min typ max unit ne5230, sa5230 offset voltage v os t a = 25 c any 0.4 3.0 mv t a = t low to t high any 3.0 4.0 drift v os any 2.0 5.0 v/ c offset current i os t a = 25 c high 3.0 50 na low 3.0 30 t a = t low to t high high 100 low 60 drift i os high 0.5 1.4 na/ c low 0.3 1.4 bias current i b t a = 25 c high 40 150 na low 20 60 t a = t low to t high high 200 low 150 drift i b high 2.0 4.0 na/ c low 2.0 4.0 supply current i s v s = 0.9 v t a = 25 c low 110 160 a high 600 750 t a = t low to t high low 250 high 800 v s = 7.5 v t a = 25 c low 320 550 a high 1100 1600 t a = t low to t high low 600 high 1700 common ? mode input range v cm v os 6 mv, t a = 25 c any v ? ? 0.25 v + + 0.25 v v os 6 mv, t a = t low to t high any v ? v + common ? mode rejection ratio cmrr v s = 7.5 v r s = 10 k ; v cm = 7.5 v; t a = 25 c any 85 95 db r s = 10 k ; v cm = 7.5 v; t a = t low to t high any 80 power supply rejection ratio psrr t a = 25 c high 90 105 db low 85 95 v os 6 mv, t a = t low to t high high 75 low 80 load current source i l v s = 0.9 v; t a = 25 c high 4.0 6 ma sink v s = 0.9 v; t a = 25 c high 5.0 7 source v s = 7.5 v; t a = 25 c high 16 sink v s = 7.5 v; t a = 25 c high 32 source v s = 0.9 v; t a = t low to t high any 1.0 5 sink v s = 0.9 v; t a = t low to t high any 2.0 6 source v s = 7.5 v; t a = t low to t high any 4.0 10 sink v s = 7.5 v; t a = t low to t high any 5.0 15 for ne5230 devices, t low = 0 c and t high = +70 c. for sa5230 devices, t low = ? 40 c and t high = +85 c.
ne5230, sa5230, se5230 http://onsemi.com 4 dc and ac electrical characteristic unless otherwise specified, 0.9v vs 7.5 v or equivalent single supply, r l = 10 k , full input common ? mode range, over full operating temperature range. characteristic unit max typ min bias test conditions symbol se5230 offset voltage v os t a = 25 c any 0.4 3.0 mv t a = t low to t high any 3.0 4.0 drift v os any 2.0 5.0 v/ c offset current i os t a = 25 c high 3.0 50 na low 3.0 30 t a = t low to t high high 100 low 60 drift i os high 0.5 1.4 na/ c low 0.3 1.4 bias current i b t a = 25 c high 40 150 na low 20 60 t a = t low to t high high 300 low 300 drift i b high 2.0 4.0 na/ c low 2.0 4.0 supply current i s v s = 0.9 v t a = 25 c low 110 160 a high 600 750 t a = t low to t high low 275 high 850 v s = 7.5 v t a = 25 c low 320 550 a high 1100 1600 t a = t low to t high low 600 high 1700 common ? mode input range v cm v os 6 mv, t a = 25 c any v ? ? 0.25 v + + 0.25 v v os 20 mv, t a = t low to t high any v ? v + common ? mode rejection ratio cmrr v s = 7.5 v r s = 10 k ; v cm = 7.5 v; t a = 25 c any 85 95 db r s = 10 k ; v cm = 7.5 v; t a = t low to t high any 80 power supply rejection ratio psrr t a = 25 c high 90 105 db low 85 95 t a = t low to t high high 75 low 80 load current source i l v s = 0.9 v; t a = 25 c high 4.0 6 ma sink v s = 0.9 v; t a = 25 c high 5.0 7 source v s = 7.5 v; t a = 25 c high 16 sink v s = 7.5 v; t a = 25 c high 32 source v s = 0.9 v; t a = t low to t high any 1.0 5 sink v s = 0.9 v; t a = t low to t high any 2.0 6 source v s = 7.5 v; t a = t low to t high any 4.0 10 sink v s = 7.5 v; t a = t low to t high any 5.0 15 for se5230 devices, t low = ? 40 c and t high = +125 c.
ne5230, sa5230, se5230 http://onsemi.com 5 dc and ac electrical characteristic unless otherwise specified, 0.9v vs 7.5 v or equivalent single supply, r l = 10 k , full input common ? mode range, over full operating temperature range. characteristic unit max typ min bias test conditions symbol ne5230, sa5230, se5230 large ? signal open ? loop gain a vol v s = 7.5 v r l = 10 k ; t a = 25 c high 120 2000 v/mv low 60 750 t a = t low to t high high 100 low 50 output voltage swing v out v s = 0.9 v t a = 25 c +sw any 750 800 mv t a = 25 c ? sw any 750 800 t a = t low to t high ; +sw any 700 t a = t low to t high ; ? sw any 700 v s = 7.5 v t a = 25 c +sw any 7.30 7.35 v t a = 25 c ? sw any ? 7.32 ? 7.35 t a = t low to t high ; +sw any 7.25 7.30 t a = t low to t high ; ? sw any ? 7.30 ? 7.35 slew rate sr t a = 25 c high 0.25 v/ s low 0.09 v/ s inverting unity gain bandwidth bw c l = 100 pf; t a = 25 c high 0.6 mhz low 0.25 mhz phase margin m c l = 100 pf; t a = 25 c any 70 settling time t s c l = 100 pf, 0.1% high 2.0 s low 5.0 s input noise v inn r s = 0 ; f = 1.0 khz high 30 nv/ hz low 60 nv/ hz total harmonic distortion thd v s = 7.5 v a v = 1; v in = 500 mv; f = 1.0 khz high 0.003 % v s = 0.9 v a v = 1, v in = 500 mv; f = 1.0 khz high 0.002 % for ne5230 devices, t low = 0 c and t high = +70 c. for sa5230 devices, t low = ? 40 c and t high = +85 c. for se5230 devices, t low = ? 40 c and t high = +125 c.
ne5230, sa5230, se5230 http://onsemi.com 6 theory of operation input stage operational amplifiers which are able to function at minimum supply voltages should have input and output stage swings capable of reaching both supply voltages within a few millivolts in order to achieve ease of quiescent biasing and to have maximum input/output signal handling capability. the input stage of the ne5230 has a common ? mode voltage range that not only includes the entire supply voltage range, but also allows either supply to be exceeded by 250 mv without increasing the input offset voltage by more than 6.0 mv. this is unequalled by any other operational amplifier today. in order to accomplish the feat of rail ? to ? rail input common ? mode range, two emitter ? coupled differential pairs are placed in parallel so that the common ? mode voltage of one can reach the positive supply rail and the other can reach the negative supply rail. the simplified schematic of figure 1 shows how the complementary emitter ? coupler transistors are configured to form the basic input stage cell. common ? mode input signal voltages in the range from 0.8 v above v ee to v cc are handled completely by the npn pair, q3 and q4, while common ? mode input signal voltages in the range of v ee to 0.8 v above v ee are processed only by the pnp pair, q1 and q2. the intermediate range of input voltages requires that both the npn and pnp pairs are operating. the collector currents of the input transistors are summed by the current combiner circuit composed of transistors q8 through q11 into one output current. transistor q8 is connected as a diode to ensure that the outputs of q2 and q4 are properly subtracted from those of q1 and q3. the input stage was designed to overcome two important problems for rail ? to ? rail capability. as the common ? mode voltage moves from the range where only the npn pair was operating to where both of the input pairs were operating, the effective transconductance would change by a factor of two. frequency compensation for the ranges where one input pair was operating would, of course, not be optimal for the range where both pairs were operating. secondly, fast changes in the common ? mode voltage would abruptly saturate and restore the emitter current sources, causing transient distortion. these problems were overcome by assuring that only the input transistor pair which is able to function properly is active. the npn pair is normally activated by the current source i b1 through q5 and the current mirror q6 and q7, assuming the pnp pair is non ? conducting. when the common ? mode input voltage passes below the reference voltage, v b1 ? 0.8 v at the base of q5, the emitter current is gradually steered toward the pnp pair, away from the npn pair. the transfer of the emitter currents between the complementary input pairs occurs in a voltage range of about 120 mv around the reference voltage v b1 . in this way the sum of the emitter currents for each of the npn and pnp transistor pairs is kept constant; this ensures that the transconductance of the parallel combination will be constant, since the transconductance of bipolar transistors is proportional to their emitter currents. an essential requirement of this kind of input stage is to minimize the changes in input of fset voltage between that of the npn and pnp transistor pair which occurs when the input common ? mode voltage crosses the internal reference voltage, v b1 . careful circuit layout with a cross ? coupled quad for each input pair has yielded a typical input offset voltage of less than 0.3 mv and a change in the input offset voltage of less than 0.1 mv. v v r10 r11 r8 r9 q3 q1 q2 q4 q10 q11 q5 q6 q7 q8 q9 v ee v cc i out v b2 + + v b1 v in ? v in+ i b1 figure 1. input stage
ne5230, sa5230, se5230 http://onsemi.com 7 output stage processing output voltage swings that nominally reach to less than 100 mv of either supply voltage can only be achieved by a pair of complementary common ? emitter connected transistors. normally, such a configuration causes complex feed ? forward signal paths that develop by combining biasing and driving which can be found in previous low supply voltage designs. the unique output stage of the ne5230 separates the functions of driving and biasing, as shown in the simplified schematic of figure 2 and has the advantage of a shorter signal path which leads to increasing the effective bandwidth. this output stage consists of two parts: the darlington output transistors and the class ab control regulator. the output transistor q3 connected with the darlington transistors q4 and q5 can source up to 10 ma to an output load. the output of npn darlington connected transistors q1 and q2 together are able to sink an output current of 10 ma. accurate and efficient class ab control is necessary to insure that none of the output transistors are ever completely cut off. this is accomplished by the differential amplifier (formed by q8 and q9) which controls the biasing of the output transistors. the dif ferential amplifier compares the summed voltages across two diodes, d1 and d2, at the base of q8 with the summed voltages across the base ? emitter diodes of the output transistors q1 and q3. the base ? emitter voltage of q3 is converted into a current by q6 and r6 and reconverted into a voltage across the base ? emitter diode of q7 and r7. the summed voltage across the base ? emitter diodes of the output transistors q3 and q1 is proportional to the logarithm of the product of the push and pull currents i op and i on , respectively. the combined voltages across diodes d1 and d2 are proportional to the logarithm of the square of the reference current i b1 . when the diode characteristics and temperatures of the pairs q1, d1 and q3, q2 are equal, the relation i op i on ? i b1 i b1 is satisfied. separating the functions of biasing and driving prevents the driving signals from becoming delayed by the biasing circuit. the output darlington transistors are directly accessible for in ? phase driving signals on the bases of q5 and q2. this is very important for simple high ? frequency compensation. the output transistors can be high ? frequency compensated by miller capacitors cm1a and cm1b connected from the collectors to the bases of the output darlington transistors. a general ? purpose op amp of this type must have enough open ? loop gain for applications when the output is driving a low resistance load. the ne5230 accomplishes this by inserting an intermediate common ? emitter stage between the input and output stages. the three stages provide a very large gain, but the op amp now has three natural dominant poles ? one at the output of each common ? emitter stage. frequency compensation is implemented with a simple scheme of nested, pole ? splitting miller integrators. the miller capacitors cm1a and cm1b are the first part of the nested structure, and provide compensation for the output and intermediate stages. a second pair of miller integrators provide pole ? splitting compensation for the pole from the input stage and the pole resulting from the compensated combination of poles from the intermediate and output stages. the result is a stable, internally ? compensated op amp with a phase margin of 70 . q5 i b1 i b2 i b3 i b5 i b4 q4 q6 q8 q9 d1 q7 q3 d2 q1 q2 r7 r6 cm1b cm1a v b2 v b5 v cc v ee v out i op i on figure 2. output stage
ne5230, sa5230, se5230 http://onsemi.com 8 thermal considerations when using the ne5230, the internal power dissipation capabilities of each package should be considered. on semiconductor does not recommend operation at die temperatures above 110 c in the so package because of its inherently smaller package mass. die temperatures of 150 c can be tolerated in all the other packages. with this in mind, the following equation can be used to estimate the die temperature: t j t amb (p d ja ) (eq. 1) where t amb = ambient temperature t j = die temperature p d = power dissipation = (i cc x v cc ) ja = package thermal resistance = 270 c/w for so ? 8 in pc board mounting see the packaging section for information regarding other methods of mounting. ja ? 100 c/w for the plastic dip. the maximum supply voltage for the part is 15 v and the typical supply current is 1.1 ma (1.6 ma max). for operation at supply voltages other than the maximum, see the data sheet for i cc versus v cc curves. the supply current is somewhat proportional to temperature and varies no more than 100 a between 25 c and either temperature extreme. operation at higher junction temperatures than that recommended is possible but will result in lower mean time between failures (mtbf). this should be considered before operating beyond recommended die temperature because of the overall reliability degradation. design techniques and applications the ne5230 is a very user ? friendly amplifier for an engineer to design into any type of system. the supply current adjust pin (pin 5) can be left open or tied through a pot or fixed resistor to the most negative supply (i.e., ground for single supply or to the negative supply for split supplies). the minimum supply current is achieved by leaving this pin open. in this state it will also decrease the bandwidth and slew rate. when tied directly to the most negative supply, the device has full bandwidth, slew rate and i cc . the programming of the current ? control pin depends on the trade ? offs which can be made in the designer ?s application. the graphs in figures 3 and 4 will help by showing bandwidth versus i cc . as can be seen, the supply current can be varied anywhere over the range of 100 a to 600 a for a supply voltage of 1.8 v. an external resistor can be inserted between the current control pin and the most negative supply. the resistor can be selected between 1.0 to 100 k to provide any required supply current over the indicated range. in addition, a small varying voltage on the bias current control pin could be used for such exotic things as changing the gain ? bandwidth for voltage controlled low pass filters or amplitude modulation. furthermore, control over the slew rate and the rise time of the amplifier can be obtained in the same manner. this con trol over the slew rate also changes the settling time and overshoot in pulse response applications. the settling time to 0.1% changes from 5.0 s at low bias to 2.0 s at high bias. the supply current control can also be utilized for wave ? shaping applications such as for pulse or triangular waveforms. the gain ? bandwidth can be varied from between 250 khz at low bias to 600 khz at high bias current. the slew rate range is 0.08 v/ s at low bias and 0.25 v/ s at high bias. figure 3. unity gain bandwidth vs. power supply current for v cc = 0.9 v figure 4. i cc current vs. bias current adjusting resistor for several supply voltages 800 700 600 500 400 300 200 100 100 200 300 400 500 600700 unity gain bandwidth (khz) t a ? 25 c v cc ? 15v v cc ? 12v v cc ? 9v v cc ? 6v v cc ? 3v v cc ? 2v v cc ? 1.8v 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 10 0 10 1 10 2 10 3 10 4 10 5 r adj ( ) power supply current ( a) i cc current (ma)
ne5230, sa5230, se5230 http://onsemi.com 9 the full output power bandwidth range for v cc equals 2.0 v, is above 40 khz for the maximum bias current setting and greater than 10 khz at the minimum bias current setting. if extremely low signal distortion (<0.05%) is required at low supply voltages, exclude the common ? mode crossover point (v b1 ) from the common ? mode signal range. this can be accomplished by proper bias selection or by using an inverting amplifier configuration. most single supply designs necessitate that the inputs to the op amp be biased between v cc and ground. this is to assure that the input signal swing is within the working common ? mode range of the amplifier. this leads to another helpful and unique property of the ne5230 that other cmos and bipolar low voltage parts cannot achieve. it is the simple fact that the input common ? mode voltage can go beyond either the positive or negative supply voltages. this benefit is made very clear in a non ? inverting voltage ? follower configuration. this is shown in figure 5 where the input sine wave allows an undistorted output sine wave which will swing less than 100 mv of either supply voltage. many competitive parts will show severe clipping caused by input common ? mode limitations. the ne5230 in this configuration offers more freedom for quiescent biasing of the inputs close to the positive supply rail where similar op amps would not allow signal processing. there are not as many considerations when designing with the ne5230 as with other devices. since the ne5230 is internally ? compensated and has a unity gain ? bandwidth of 600 khz, board layout is not so stringent as for very high frequency devices such as the ne5205. the output capability of the ne5230 allows it to drive relatively high capacitive loads and small resistive loads. the power supply pins should be decoupled with a low ? pass rc network as close to the supply pins as possible to eliminate 60 hz and other external power line noise, although the power supply rejection ratio (psrr) for the part is very high. the pinout for the ne5230 is the same as the standard single op amp pinout with the exception of the bias current adjusting pin. v+ v ? + ? ne5230 other parts v+ v ? v+ v ? v+ v ? figure 5. in a non ? inverting voltage ? follower configuration, the ne5230 will give full rail ? to ? rail swing. other low voltage amplifiers will not because they are limited by their input common ? mode range and output swing capability.
ne5230, sa5230, se5230 http://onsemi.com 10 remote transducer with current transmission there are many ways to transmit information along two wires, but current transmission is the most beneficial when the sensing of remote signals is the aim. it is further enhanced in the form of 4.0 to 20 ma information which is used in many control ? type systems. this method of transmission provides immunity from line voltage drops, large load resistance variations, and voltage noise pickup. the zero reference of 4ma not only can show if there is a break in the line when no current is flowing, but also can power the transducer at the remote location. usually the transducer itself is not equipped to provide for the current transmission. the unique features of the ne5230 can provide high output current capability coupled with low power consumption. it can be remotely connected to the transducer to create a current loop with minimal external components. the circuits for this are shown in figures 6 and 7. here, the part is configured as a voltage ? to ? current, or transconductance amplifier. this is a novel circuit that takes advantage of the ne5230?s large open ? loop gain. in ac applications, the load current will decrease as the open ? loop gain rolls off in magnitude. the low offset voltage and current sinking capabilities of the ne5230 must also be considered in this application. the ne5230 circuit shown in figure 6 is a pseudo transistor configuration. the inverting input is equivalent to the ?base,? the point where v ee and the non ? inverting input meet is the ?emitter,? and the connection after the output diode meets the v cc pin is the collector. the output diode is essential to keep the output from saturating in this configuration. from here it can be seen that the base and emitter form a voltage ? follower and the voltage present at r c must equal the input voltage present at the inverting input. also, the emitter and collector form a current ? follower and the current flowing through r c is equivalent to the current through r l and the amplifier. this sets up the current loop. therefore, the following equation can be formulated for the working current transmission line. the load current is: i l v in r c (eq. 2) and proportional to the input voltage for a set r c . also, the current is constant no matter what load resistance is used while within the operating bandwidth range of the op amp. when the ne5230?s supply voltage falls past a certain point, the current cannot remain constant. this is the ?voltage compliance? and is very good for this application because of the near rail output voltage. the equation that determines the voltage compliance as well as the largest possible load resistor for the ne5230 is as follows: r lmax [ v remote supply v cc min v in max ] i l (eq. 3) where v cc min is the worst ? case power supply voltage (approximately 1.8 v) that will still keep the part operational. as an example, when using a 15 v remote power supply, a current sensing resistor of 1.0 , and an input voltage (v in ) of 20 mv, the output current (i l ) is 20 ma. furthermore, a load resistance of zero to approximately 650 can be inserted in the loop without any change in current when the bias current ? control pin is tied to the negative supply pin. the voltage drop across the load and line resistance will not af fect the ne5230 because it will operate down to 1.8 v. with a 15 v remote supply, the voltage available at the amplifier is still enough to power it with the maximum 20 ma output into the 650 load. figure 6. the ne5230 as a remote transducer transconductance amp with 4.0 ? 20 ma current transmission output capability t r a n s d u c e r v remote power supply ne5230 v cc v ee v in i out 3 2 4 5 6 7 + ? r c r l + ? notes: 1. i out = v in/rc 2. r l max v remote 1.8v v inmax i out for r c = 1.0 i out 4ma v in 4mv 20ma 20mv figure 7. the same type of circuit as figure 6, but for sourcing current to the load v cc ne5230 3 2 4 5 6 7 + ? v ee + i out + ? v in r c r l v cc + ?
ne5230, sa5230, se5230 http://onsemi.com 11 what this means is that several instruments, such as a chart recorder, a meter, or a controller, as well as a long cable, can be connected in series on the loop and still obtain accurate readings if the total resistance does not exceed 650 . furthermore, any variation of resistance in this range will not change the output current. any voltage output type transducer can be used, but one that does not need external dc voltage or current excitation to limit the maximum possible load resistance is preferable. even this problem can be surmounted if the supply power needed by the transducer is compatible with the ne5230. the power goes up the line to the transducer and amplifier while the transducer signal is sent back via the current output of the ne5230 transconductance configuration. the voltage range on the input can be changed for transducers that produce a large output by simply increasing the current sense resistor to get the corresponding 4.0 to 20 ma output current. if a very long line is used which causes high line resistance, a current repeater could be inserted into the line. the same configuration of figure 7 can be used with exception of a resistor across the input and line ground to convert the current back to voltage. again, the current sensing resistor will set up the transconductance and the part will receive power from the line. temperature transducer a variation on the previous circuit makes use of the supply current control pin. the voltage present at this pin is proportional to absolute temperature (ptat) because it is produced by the amplifier bias current through an internal resistor divider in a ptat cell. if the control pin is connected to the input pin, the ne5230 itself can be used as a temperature transducer . if the center tap of a resistive pot is connected to the control pin with one side to ground and the other to the inverting input, the voltage can be changed to give different temperature versus output current conditions (figure 8). for additional control, the output current is still proportional to the input voltage differential divided by the current sense resistor. when using the ne5230 as a temperature transducer, the thermal considerations in the previous section must be kept in mind. v remote power supply ne5230 v cc v ee i out 3 2 4 5 6 7 + ? r c r l + ? notes: 1. i out = v in/rc 2. r l max v remote 1.8v v inmax i out for r c = 1 i out 4ma 20ma v in 4mv 20mv 200 figure 8. ne5230 remote temperature transducer utilizing 4.0 ? 20 ma current transmission. this application shows the use of the accessibility of the ptat cell in the device to make the part, itself, a transducer. 10
ne5230, sa5230, se5230 http://onsemi.com 12 half ? wave rectifier with rail ? to ? ground output swing since the ne5230 input common ? mode range includes both positive and negative supply rails and the output can also swing to either supply, achieving half ? wave rectifier functions in either direction becomes a simple task. all that is needed are two external resistors; there is no need for diodes or matched resistors. moreover, it can have either positive ? or negative ? going outputs, depending on the way the bias is arranged. in figure 9, the circuit is biased to ground, while circuit (figure 10) is biased to the positive supply. this rather unusual biasing does not cause any problems with the ne5230 because of the unique internal saturation detectors incorporated into the part to keep the pnp and npn output transistors out of ?hard? saturation. it is therefore relatively quick to recover from a saturated output condition. furthermore, the device does not have parasitic current draw when the output is biased to either rail. this makes it possible to bias the ne5230 into ?saturation? and obtain half ? wave rectification with good recovery. the simplicity of biasing and the rail ? to ? ground half ? sine wave swing are unique to this device. the circuit gain can be changed by the standard op amp gain equations for an inverting configuration. it can be seen in these configurations that the op amp cannot respond to one ? half of the incoming waveform. it cannot respond because the waveform forces the amplifier to swing the output beyond either ground or the positive supply rail, depending on the biasing, and, also, the output cannot disengage during this half cycle. during the other half cycle, however, the amplifier achieves a half ? wave that can have a peak equal to the total supply voltage. the photographs in figure 11 show the effect of the different biasing schemes, as well as the wide bandwidth (it works over the full audio range), that the ne5230 can achieve in this configuration. v cc figure 9. rail ? to ? ground output swing referenced to ground figure 10. negative ? going output referenced to v cc v in v cc 2 3 4 5 6 7 ? + o t v cc v out t v cc 3 2 4 5 6 7 v in v out v cc ? + half ? wave rectifier with positive ? going output swings 10 10 10 10
ne5230, sa5230, se5230 http://onsemi.com 13 500 mv/div 200 s /div biased to ground 500 mv/div 20 s/div biased to ground 500 mv/div 20 s/div biased to positive rail figure 11. performance waveforms for the circuits in figures 9 and 10. good response is shown at 1.0 and 10 khz for both circuits under full swing with a 2.0 v supply.
ne5230, sa5230, se5230 http://onsemi.com 14 by adding another ne5230 in an inverting summer configuration at the output of the half ? wave rectifier, a full ? wave can be realized. the values for the input and feedback resistors must be chosen so that each peak will have equal amplitudes. a table for calculating values is included in figure 12. the summing network combines the input signal at the half ? wave and adds it to double the half ? wave?s output, resulting in the full ? wave. the output waveform can be referenced to the supply or ground, depending on the half ? wave configuration. again, no diodes are needed to achieve the rectification. this circuit could be used in conjunction with the remote transducer to convert a received ac output signal into a dc level at the full ? wave output for meters or chart recorders that need dc levels. half-wave a b +v in ? v in a b +v in ? v in ab +v in +v b full-wave 2a ? 2v in 0 v ee v ee v cc +v b r1 3 2 4 5 6 7 r2 r3 r5 r4 2 3 4 5 6 7 + ? + ? a 1 a 2 input half-wave output full-wave output 500mv 500mv 500mv 520 s notes: r2 = 2 r1 r4 = r5 = r3 +v b will vary output reference. for single supply operation v ee can be grounded on a2. figure 12. adding an inverting summer to the input and output of the half ? wave will result in full ? wave
ne5230, sa5230, se5230 http://onsemi.com 15 conclusion the ne5230 is a versatile op amp in its own right. the part was designed to give low voltage and low power operation without the limitations of previously available amplifiers that had a multitude of problems. the previous application examples are unique to this amplifier and save the user money by excluding various passive components that would have been needed if not for the ne5230?s special input and output stages. the ne5230 has a combination of novel specifications which allows the designer to implement it easily into existing low ? supply voltage designs and to enhance their performance. it also offers the engineer the freedom to achieve greater amplifier system design goals. the low input referenced noise voltage eases the restrictions on designs where s/n ratios are important. the wide full ? power bandwidth and output load handling capability allow it to fit into porta ble audio applications. the truly ample open ? loop gain and low power consumption easily lend themselves to the requirements of remote transducer applications. the low, untrimmed typical offset voltage and low offset currents help to reduce errors in signal processing designs. the amplifier is well isolated from changes on the supply lines by its typical power supply rejection ratio of 105 db. references 1. johan h. huijsing, multi ? stage amplifier with capacitive nesting for frequency compensation , u.s. patent application serial no. 602.234, filed april 19, 1984. 2. bob blauschild, differential amplifier with rail ? to ? rail capability , u.s. patent application serial no. 525.181, filed august 23, 1983. 3. operational amplifiers ? characteristics and applications , robert g. irvine, prentice ? hall, inc., englewood cliffs, nj 07632, 1981. 4. transducer interface handbook ? a guide to analog signal conditioning , edited by daniel h. sheingold, analog devices, inc., norwood, ma 02062, 1981.
ne5230, sa5230, se5230 http://onsemi.com 16 ne5230n awl yywwg sa5230n awl yywwg pdip ? 8 n suffix case 626 soic ? 8 d suffix case 751 a = assembly location wl, l = wafer lot yy, y = year ww, w = work week g or = pb ? free package marking diagrams n5230 alyw 1 8 s5230 alyw 1 8 s5230 alywe 1 8 ordering information device description temperature range shipping ? ne5230d 8 ? pin plastic small outline (so ? 8) package 0 c to +70 c 98 units / rail ne5230dg 8 ? pin plastic small outline (so ? 8) package (pb ? free) 0 c to +70 c 98 units / rail ne5230dr2 8 ? pin plastic small outline (so ? 8) package 0 c to +70 c 2500 / tape & reel NE5230DR2G 8 ? pin plastic small outline (so ? 8) package (pb ? free) 0 c to +70 c 2500 / tape & reel ne5230n 8 ? pin plastic dual in ? line package (pdip ? 8) 0 c to +70 c 50 units / rail ne5230ng 8 ? pin plastic dual in ? line package (pdip ? 8) (pb ? free) 0 c to +70 c 50 units / rail sa5230d 8 ? pin plastic small outline (so ? 8) package ? 40 c to +85 c 98 units / rail sa5230dg 8 ? pin plastic small outline (so ? 8) package (pb ? free) ? 40 c to +85 c 98 units / rail sa5230dr2 8 ? pin plastic small outline (so ? 8) package ? 40 c to +85 c 2500 / tape & reel sa5230dr2g 8 ? pin plastic small outline (so ? 8) package (pb ? free) ? 40 c to +85 c 2500 / tape & reel sa5230n 8 ? pin plastic dual in ? line package (pdip ? 8) ? 40 c to +85 c 50 units / rail sa5230ng 8 ? pin plastic dual in ? line package (pdip ? 8) (pb ? free) ? 40 c to +85 c 50 units / rail se5230d 8 ? pin plastic small outline (so ? 8) package ? 40 c to +125 c 98 units / rail se5230dr2 8 ? pin plastic small outline (so ? 8) package ? 40 c to +125 c 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ne5230, sa5230, se5230 http://onsemi.com 17 package dimensions notes: 1. dimension l to center of lead when formed parallel. 2. package contour optional (round or square corners). 3. dimensioning and tolerancing per ansi y14.5m, 1982. 14 5 8 f note 2 ? a ? ? b ? ? t ? seating plane h j g d k n c l m m a m 0.13 (0.005) b m t dim min max min max inches millimeters a 9.40 10.16 0.370 0.400 b 6.10 6.60 0.240 0.260 c 3.94 4.45 0.155 0.175 d 0.38 0.51 0.015 0.020 f 1.02 1.78 0.040 0.070 g 2.54 bsc 0.100 bsc h 0.76 1.27 0.030 0.050 j 0.20 0.30 0.008 0.012 k 2.92 3.43 0.115 0.135 l 7.62 bsc 0.300 bsc m ??? 10 ??? 10 n 0.76 1.01 0.030 0.040 pdip ? 8 case 626 ? 05 issue l
ne5230, sa5230, se5230 http://onsemi.com 18 package dimensions soic ? 8 nb case 751 ? 07 issue ag seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751 ? 01 thru 751 ? 06 are obsolete. new standard is 751 ? 07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ? x ? ? y ? g m y m 0.25 (0.010) ? z ? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?t ypicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license un der its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended f or surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in a ny manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2 ? 9 ? 1 kamimeguro, meguro ? ku, tokyo, japan 153 ? 0051 phone : 81 ? 3 ? 5773 ? 3850 ne5230/d literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082 ? 1312 usa phone : 480 ? 829 ? 7710 or 800 ? 344 ? 3860 toll free usa/canada fax : 480 ? 829 ? 7709 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.

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